//--------------------------------------------------------------------------------------------
//    : 
//      Component name  : fpadd_stage5
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPadd_stage5(EXP_norm, OV_stage4, SIG_norm, Z_SIGN_stage4, clk, isINF_tab_stage4, isNaN_stage4, isZ_tab_stage4, zero_stage4, OV, SIG_norm2, Z_EXP, Z_SIGN, isINF_tab, isNaN, isZ_tab, zero);
   input [7:0]   EXP_norm;
   input         OV_stage4;
   input [27:0]  SIG_norm;
   input         Z_SIGN_stage4;
   input         clk;
   input         isINF_tab_stage4;
   input         isNaN_stage4;
   input         isZ_tab_stage4;
   input         zero_stage4;
   output        OV;
   reg           OV;
   output [27:0] SIG_norm2;
   reg [27:0]    SIG_norm2;
   output [7:0]  Z_EXP;
   reg [7:0]     Z_EXP;
   output        Z_SIGN;
   reg           Z_SIGN;
   output        isINF_tab;
   reg           isINF_tab;
   output        isNaN;
   reg           isNaN;
   output        isZ_tab;
   reg           isZ_tab;
   output        zero;
   reg           zero;
   
   
   wire [7:0]    EXP_round_int;
   wire [27:0]   SIG_norm2_int;
   wire [27:0]   SIG_round_int;
   wire [7:0]    Z_EXP_int;
   
   
   always @(posedge clk)
      
      begin
         Z_EXP <= Z_EXP_int;
         SIG_norm2 <= SIG_norm2_int;
         Z_SIGN <= Z_SIGN_stage4;
         OV <= OV_stage4;
         zero <= zero_stage4;
         isINF_tab <= isINF_tab_stage4;
         isNaN <= isNaN_stage4;
         isZ_tab <= isZ_tab_stage4;
      end
   
   
   FPnormalize #(.SIG_width(28)) I11(.SIG_in(SIG_round_int), .EXP_in(EXP_round_int), .SIG_out(SIG_norm2_int), .EXP_out(Z_EXP_int));
   
   FPround #(.SIG_width(28)) I10(.SIG_in(SIG_norm), .EXP_in(EXP_norm), .SIG_out(SIG_round_int), .EXP_out(EXP_round_int));
   
endmodule
